1. Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for detecting and correcting instruction fetch errors within a processor core.
2. Description of the Related Art
During normal operation, uncorrectable data errors encountered during the execution of a program are fatal to the whole system. With higher levels of integration in CPUs and ever smaller geometries, each occurrence of a fatal error detracts from the availability of the system. An additional implication is that with usage models such as virtual threading (“VT”), the “system” consists of a number of virtual machines (“VMs”) which, for all intents and purposes, are running independent of each other. Therefore, when the system is brought down because of an error that occurred in one VM, it means that all VMs running on that system are brought down.
By way of example, in prior art Intel Architecture-32 (IA32) systems, uncorrected data errors encountered anywhere in the memory hierarchy during an instruction fetch or data fetch are immediately fatal. When such errors are encountered, the processor core logs a fatal error and signals the event immediately. The only action available to an OS or hypervisor at this point would is to bring down the whole system.
Consequently, it would be beneficial to design a system in which uncorrectable data errors during instruction fetch and/r data fetch can be isolated to the offending VM or application so that only that portion of the system implicated in the error is brought down, leaving all the others operational.